The reduction of power consumption is an important aspect of high performance microprocessor design. Clock gating reduces power consumption by gating a clock signal when it is not required. Clock gating is typically implemented in the design phase of a circuit by grouping flip-flops that share the same gating function to a clock gating header. The clock gating header receives as input the clock signal and an enable signal that corresponds to the gating function. The clock gating header outputs the gated clock signal to the individual flip-flops of the group in accordance with the gating function.